Clone Circuit Board Layout Design Through Hole Drill File Side Effect

The greatest side effect of Clone Circuit Board Layout Design Through Hole Drill File is the parasitic capacitance to ground;

Clone Circuit Board Layout Design Through Hole Drill File Side Effect

The via itself has a parasitic capacitance to ground. If the diameter of the isolation hole of the via on the ground layer is known as D2,
The diameter of the via pad is D1,
The thickness of the PCB board is T,
The dielectric constant of the board substrate is ε,
Then the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1)

The main effect of the parasitic capacitance of the via on the circuit is to extend the rise time of the signal and reduce the speed of the circuit.
For example, for a PCB board with a thickness of 50 Mil, if a via with an inner diameter of 10 Mil and a pad diameter of 20 Mil is used, the distance between the pad and the ground copper area is 32 Mil,
Then we can approximate the parasitic capacitance of the via via the above formula: C=1.41×4.4×0.050×0.020/(0.032-0.020)=0.517pF,

The rise time variation caused by this part of capacitance is: T10-90=2.2C(Z0/2)=2.2×0.517x(55/2)=31.28ps.

It can be seen from these values that although the effect of slowing the rise delay caused by the parasitic capacitance of a single via is not very obvious,

However, if you use vias for switching between layers multiple times in the trace, the designer must carefully consider.